The present invention relates to speakers for personal computers and particularly to an architecture for a Universal Serial Bus-based PC speaker controller having noise elimination circuitry.
The Universal Serial Bus (USB) specification is a proposed standard recently promulgated by a group of computer companies including Compaq Computer Corporation, Digital Equipment Corporation, IBM, Intel Corporation, Microsoft Corporation and Northern Telecom. Described below are various aspects of the Universal Serial Bus. Further background concerning the Universal Serial Bus may be obtained from the Universal Serial Bus Specification, Revision 1.0, which is hereby incorporated by reference. The Universal Serial Bus is intended as a bidirectional, isochronous, low-cost, dynamically attachable, serial interface to promote easy PC peripheral expansion and provide full support for real-time voice, audio, and compressed video data. The Universal Serial Bus provides two-wire point-to-point signaling in which the signals are differentially driven at a bit rate of 12 megabits per second. The Universal Serial Bus includes support for both isochronous and asynchronous messaging at the 12 megabit per second data speed.
The Universal Serial Bus specification defines a Universal Serial Bus system in terms of Universal Serial Bus xe2x80x9cinterconnectsxe2x80x9d, xe2x80x9cdevicesxe2x80x9d, and xe2x80x9chostsxe2x80x9d. A Universal Serial Bus interconnect defines the manner in which devices are connected to and communicate with the host, including bus topology, data flow models, scheduling, and interlayer relationships. In any given Universal Serial Bus topology, there is only one host.
Universal Serial Bus devices include hubs and functions. Hubs provide additional attachment points to the Universal Serial Bus and may be integrated with a host, which ordinarily provides only one attachment point for connecting a hub or a function. Functions provide capabilities to the system, such as joystick, keyboard, microphone, and speaker capabilities.
The basic data transfer protocol of the Universal Serial Bus is described as follows, with particular attention to FIG. 1. FIG. 1 is a diagram of the basic packet transfer 1000 of the Universal Serial Bus. The basic transfer 1000 includes a token packet 1002, a data packet 1004, and a handshake packet 1006. Each packet is preceded by a synchronization field SYNC which is used by input circuitry to align incoming data with the local clock. It is defined to be 8 bits in length and is stripped out by the connector interface.
Following the SYNC field in each packet is a packet identifier (PID(T) for the token packet, PID(D) for the data packet, PID(H) for the handshake packet, and PID(S) for the start-of-frame packet, which may be considered a type of token packet). The packet identifiers PID(T), PID(D), PID(H) and PID(S) include a 4-bit identification field and a 4-bit check field used to identify the format of the packet and type. There are two types of token 1002 packet ID fields PID(T). These denote (i) a data transfer from the function to the host; and (ii) a data transfer from the host to the function. In addition to the packet ID, PID(T), the token packet includes an 8-bit address field ADDR and a 3-bit end point field, ENDP. The address field ADDR of the token packet specifies the function that it is to receive or send the data packet. The end-point field ENDP permits addressing of more than one subchannel of an individual function.
Only one type of start-of-frame packet identification field 1008, PID(S), is defined: a start of frame time stamp. The address and endpoint fields of the token packet are replaced in the start of frame packet with a time-stamp field. The time-stamp field for the start of frame packet provides a clock tick which is available to all devices on the bus. The start-of-frame packet is sent by the host every 1 msxc2x10.01%. In addition, for both the token and start-of-frame packets, a 5-bit cyclical redundancy checksum (CRC) field is provided.
The data packet 1004 includes a packet identifier PID(D), a data field DATA, and a 16-bit cyclical redundancy checksum field, CRC16. Two types of packet IDs for the data field, data 0 and data 1, identify whether the data packet is being sent for the first time or whether being sent as a retry. The data field DATA may vary in length from 0 to N bytes. Failure of the cyclical redundancy checksum on the data field DATA causes the receiver to issue an error ERR handshake.
The handshake packet 1006 includes only a packet identifier PID(H), of which there are four types. An acknowledge handshake, ACK, indicates that the receiver will accept the data and that the CRC has succeeded. A negative acknowledge, NACK, indicates that the receiver cannot accept the data or that the source cannot send the data. An ERR field indicates that the receiver will accept the data, but that the CRC has failed. A stall handshake packet, STALL, indicates that the transmission or reception pipe is stalled. A stall handshake is defined only for stream-oriented end-points (as distinguished from message-oriented endpoints, discussed below).
Data flow on the Universal Serial Bus is defined in terms of xe2x80x9cpipes.xe2x80x9d A pipe is a connection between a host and an endpoint. The Universal Serial Bus defines xe2x80x9cstreamxe2x80x9d and xe2x80x9cmessagexe2x80x9d pipes. For a stream pipe, data is delivered in prenegotiated packet sizes. Data flows in at one end of the stream pipe and out the other end in the same order. Stream mode thus includes flow control and employs no defined USB structure. For a message pipe, however, a request is first sent to the device which is followed at some later time by a response from the end-point. Message pipes thus impose a structure on the data flow, which allows commands to be communicated. These commands can include band-width allocation.
The Universal Serial Bus supports isochronous, asynchronous, and asynchronous interactive data flow. For isochronous data, access to USB bandwidth is guaranteed. A constant data rate through the pipe is provided, and in the case of delivery failure due to error, there is no attempt to retry to deliver the data. Asynchronous interactive data flow provides a guaranteed service rate for the pipe, and the retry of failed transfer attempts. Asynchronous data flow accommodates access to the USB on a band-width available basis and also permits retry of data transfers.
Scheduling of the Universal Serial Bus is defined in terms ofxe2x80x9cslotsxe2x80x9d, xe2x80x9cframesxe2x80x9d and xe2x80x9csuper framesxe2x80x9d, as illustrated in FIG. 2, which shows an exemplary USB schedule 1100. Frames 1104a and 1104b begin with a start of frame packet, 1108a and 1108b, respectively. Each frame has a duration of time equal to 1xc2x1N ms. Each frame, 1104b, 1104b is subdivided into one or more slots, 1102a, 1102b, for example. Each slot corresponds to some USB transaction, e.g., 1110a, 1110b, 1110c, 1110d. Each slot is large enough to contain the worst case transmission time of the transaction to which it corresponds, and includes the effects of bit-stuffing, propagation delay through cables and hubs, response delays, and clocking differences between the host and the end-point. A super frame 1106 consists of a repeatable sequence of individual frames, and is the largest schedulable portion of time permitted.
The Universal Serial Bus provides both periodic service and aperiodic service. For periodic service corresponding to isochronous data, a fixed period exists between the delivery of start of frame packets to a specific end-point. However, aperiodic service is characterized by a varying period between delivery of start of frame tokens for a given end-point. Periodic service is given a higher priority in scheduling than aperiodic service.
Turning now to FIG. 3, there is illustrated an abstracted block diagram of a Universal Serial Bus device, such as a hub or function. Universal Serial Bus device 1200 includes a device interface 1202 and a class interface 1204. Device interface 1202 includes device information and control block 1206, which is required for the USB device to attach to the USB and is independent of the functionality provided by the device. The device interface further includes serial bus interface engine 1210, which provide for management of the bus interface, including performing acknowledgments and recognizing packets that are addressed to the USB device. In addition, the interface engine 1210 provides for stripping the SYNC field from incoming packets. The class interface 1204 includes class information and control block 1214 which depends upon the functionality of the device (for example, hubs and locators). Class interface 1204 further includes function engine 1216 which relates to the functionality implemented by the device. A USB device further includes logical buffers, such as packet buffer 1208 and elasticity buffer 1212. The packet buffer defines the maximum packet size which the USB device can receive or send. The elasticity buffer relates to how flexible the scheduled generator may be in allocating band-width for the associated end-point and determines the maximum amount of data the device end-point can handle. The various functional blocks of the USB device are not shown connected to one another in FIG. 3 because, as discussed in the USB specification, the relationship among the components may be implementation-dependent. In addition, a Universal Serial Bus device may include storage space, local to the USB device, though addressable by the host; and vendor space, which may be defined by the vendor of the device.
While the Universal Serial Bus is intended to be an industry-wide standard peripheral interface, the Universal Serial Bus Specification does not define the relationship among components in Universal Serial Bus devices. There is therefore a need to provide novel architectures for Universal Serial Bus devices. More particularly, there is a need to define a novel architecture for a powered speaker and/or microphone compatible with the Universal Serial Bus Specification.
In addition, while the USB specification defines signaling whereby a USB device or hub controller may wake the network from a low power mode, the USB specification does not define a mechanism whereby the devices may power themselves down or awaken in response to the signaling. There is therefore a need to provide a USB compatible speaker and/or microphone having power management capabilities.
Moreover, in the case of a USB speaker and/or microphone, random power fluctuations, either at power-up or during normal operation, can feed through the speakers and cause annoying xe2x80x9cpopsxe2x80x9d and xe2x80x9chissesxe2x80x9d to be transmitted through the speakers. In the extreme case, these can cause damage to the speaker. Accordingly, there is a need to provide a USB compatible speaker and/or microphone having click suppression when the USB is unstable or during power-up and power-down.
Accordingly, there is provided a novel powered loudspeaker implemented to be compatible with a serial bus standard and, particularly, the Universal Serial Bus specification. The powered speaker includes a speaker driven by a power amplifier coupled to a power supply. Both the amplifier and the power supply, in turn, are coupled to a Universal Serial Bus controller. The controller is configured to provide Universal Serial Bus functionality and compatibility. In addition, a phase locked loop (PLL) for recovering a timer clock from the received data stream is provided. One embodiment of the present system further includes a function whereby the absence of data on the relevant channel is detected and the output to the speakers is muted in response thereto. A further circuit is provided that controls when the output to the speaker is turned on such that no clicks or pops occur at power-up or when the device or bus is not stable. In addition, tone control, including bass and treble filters, volume control, and balance between left and right outputs (in a stereo version) are provided. Furthermore, power management functionality is provided. If the USB has been idle for a predetermined period of time, the system can place itself into a low power sleep mode, or the loudspeaker can be placed into a sleep mode via software from the host.
A microphone compatible with the Universal Serial Bus specification may also be provided, either as a discrete unit or integrated with the loudspeaker. The microphone includes a microphone input driving an amplifier coupled to a power feed and gain control. Both are coupled to audio data circuitry, which includes an analog-to-digital converter and various filters, tone and volume control, and a circuit for providing 3D audio effects. Both the gain control and the audio data block are coupled to a Universal Serial Bus controller. The controller is configured to provide Universal Serial Bus functionality and compatibility. In addition, a circuit for integrating the microphone signal into an isochronous USB signal is provided.
A power control circuit for use with a USB microphone/speaker includes a mechanism for monitoring activity on the Universal Serial Bus. If the USB has been idle for a predetermined period, the control mechanism will power down the speaker. For example, the circuit may be configured to monitor activity levels on a particular channel of the USB. If the activity levels are below a predetermined threshold for a predetermined period, the control circuit will cause the power to the device to shut off or down. In this power down state, however, the circuit will monitor the bus for host signals indicating that the speaker is to be powered up once more. In the case of the microphone, the circuit will also monitor the audio input and cause the microphone to power up in response to receiving an input signal. Circuitry is also provided for the microphone to awaken the rest of the system. Circuitry may also be provided to monitor the level and duration of the input signal. Thus, the microphone will not power up unless the input exceeds a predetermined activity and duration threshold. In this way, the microphone will not waken the network to process transient undesired inputs.
As noted above, one problem with controlling power to loudspeakers is that of voltage transients causing hisses or clicks. Accordingly, there is provided a mechanism to monitor the DC voltage level and turn off the power if it goes below a predetermined threshold. The volume is ramped to zero after which power may be turned off. After a predetermined time, allowing the transient to subside, the volume may be ramped back to the original level. In addition to monitoring the DC voltage level, the circuit will monitor the cyclical redundancy checksum for failure and look for random noise signals. Either can be a source of clicks or hisses. Once either is detected, the circuit will ramp the volume down; after a predetermined time, volume will be ramped back to the original level. In another embodiment, the monitoring circuit will continue monitoring while the volume is down and, when the error condition is no longer detected, restore the volume to its original level. In addition, high pass filtering may be provided to reject low frequency noise.